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VHDL语言实现的arm内核
- 5个ram核,arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核,verilog写的,有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心,结构良好,简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目,国防科技大学牛人ShengYu Shen写的,原来放在opencores上,
DUC.rar
- 基于XILINX ISE下的数字上变频设计,其中用到了XILINX的乘法IP。已经通过工程实用,好用。,XILINX ISE based on frequency of figure design, use one of the XILINX multiplication IP. Has passed the project practical, easy to use.
SRAM
- 使用方法: SRAM编程,拷贝到硬盘,用ISE打开工程文件即可-Usage: SRAM programming, copied to the hard drive, open the project file with ISE can
canbus
- CAN总线的FPGA实现,用Verilog编写,代码完整,而且有很完善的测试代码,用ISE直接打开,学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
fpga-dm9000a
- 一个项目工程,硬件包含XINLINX FPGA,配置FLASH,串口,SDRAM,与以太网芯片DM9000A,实现数据采集,以太网传输,电路验证完全正确,请放心使用,SPARTAN 3E 的BGA引脚320个,不容易布板,可以参考使用的。要FPGA实现网络通信也可以参考电路,B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SD
T-REC-H.264-200503-S!!PDF-C
- H.264中文版的翻译,希望对大家有帮助,我从网上找的,发在这里,待阿可以免费下载·-H.264 chinese translation version, wish this can help you in your design and project@
GPS.RAR
- 本工程包含了一个GPS接收机的基带处理模块,包括信号捕获和跟踪、电文解调等-The project includes a GPS receiver baseband processing modules, including signal acquisition and tracking, message demodulation
YCbCr_RGB_10bit
- YCbCr 转 RGB模块,以应用于项目中。 该模块可将10bitYCbCr分量视频转换为12bitRGB视频,需消耗乘法器。-YCbCr turn RGB module, to apply to the project. The module can be 10bitYCbCr component video converted to 12bitRGB video, need to consume multiplier.
AssignmentP3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx
EP1C3_12_5_RSV
- 基于FPGA的数字存储示波器,用VHDL实现的,压缩包里是Quartus工程。AD采样送进FPGA,存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
E1-FramerDeframer
- E1 Framer/Deframer,E1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note:This project is part of the OpenStacks initiative at the Telecom Software Laborator
crc
- 自己写的循环冗余校验,进行了仿真,整个工程都在!-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
Project
- 基于SOPC实现的俄罗斯方块,用VGA来做显示,PS2键盘来控制-SOPC-based implementation of Tetris, to do with the VGA display, PS2 keyboard to control the
3
- vhdl项目设置: flv的 -VHDL Project Settings: flv
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
davincihd_revf_ver6
- DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码,是Spectrum Digital, Inc刚开发出来的! CPLD Firmware Project CPLD Firmware Project (Version 6).-DaVinci HD CPLD Firmware Resources This is the original TI development board DM6467 Schema
ramvhdllib_06
- The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
SONET_Framer
- The framer project assignment consists in developing a receiver for detecting SONET Frames patterns. Its basic functions are to receive a stream of serial data and based on SONET frames protocol build the sonet frames that carry the information da
UART
- 使用方法: uart编程,拷贝到硬盘,用ISE打开工程文件即可-Usage: uart programming, copied to the hard drive, open the project file with ISE can
Chapter10
- 使用方法: 以太网编程,拷贝到硬盘,用ISE打开工程文件即可-Usage: Ethernet programming, copied to the hard drive, open the project file with ISE can